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Job Location | Bangalore |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | Consumer Durables / Electronics |
Functional Area | Sales / BD |
EmploymentType | Full-time |
Position Description: To be part of a highly skilled and challenging high speed PHY design team working on the newest technology nodes (12nm and below). Responsible for overall IP and sub- system verification from test plan creation, UVM development to signoff. Ensure first pass product through multi- dimensional verification coverage including mixed mode verification. Leading, mentoring and coaching junior team members Pair with similar domain specialists across other geographical locations on core technical initiatives Work closely with Digital and Analog designers Equal opportunity position with excellent pay package! SKILLS required: Strong knowledge of DDR/LPDDR JEDEC and DFI protocols Exposure to verification of complex high speed PHY and/or complex AMS IPs Proven track record of building testplan, UVM environment and testbenches Experience with RTL debugging, score boarding and code coverage analysis Sound knowledge of Verilog and System Verilog languages Exposure to modelling and validating complex analog circuits in Verilog and Verilog- A Experience of complex mixed signal design verification using state of the art flows and tools The position requires good written verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams. Team leadership experience, including planning and managing tasks is desirable M.S./M.Tech, BS/BE (Electronics),
Keyskills :
verbal communication design verificationanalog circuits javacode coverage asic verificationsignal design