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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
-Looking for Front- end Digital design engineers who are conversant with RTL design using System Verilog/ SystemC.Should be well versed with different areas of digital design, RTL coding, micro- architecture development, Low- power design techniques, simulation, synthesis, scripting.Should be a team player who is willing to work with Verif/ Back- end/ Power/ Architecture teams.1. Masters/ Bachelors in Electronics Engineering 2. Digital design skills (FPGA/ ASIC), Low- power aware design , Micro- architecture design skills 3. Hardware Description Language: SystemVerilog/ Verilog/ SystemC 4. Scripting Languages - Perl/ Python 5. Knowledge in Deep Learning would be advantageous, not mandatory 6. Team Player,
Keyskills :
cadencestatic timing analysis asicasic design drcfront end rtl designrtl coding deep le